Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are commonly used as power devices in applications, such as automotive electronics, power supplies, telecommunications, which applications require devices to operate at currents in the range of tenths up to hundreds of amperes (A).
Conventionally, by applying a voltage to the gate electrode of a MOSFET device, a channel will be formed connecting the source and the drain regions allowing a current to flow. Once the MOSFET device is turned on, the relation between the current and the voltage is nearly linear which means that the device behaves like a resistance. The resistance is referred to as the on-state resistance Rdson.
Typically, power MOSFET devices with low on-state resistance Rdson are preferred as they have higher current capability. In the power MOSFET devices typically a plurality of transistor base cells are arranged in parallel for reducing the Rdson and the on-state resistance Rdson may be decreased by increasing the packing density of a power MOSFET device i.e. the number of base cells per cm2. The plurality of parallel arranged transistor base cells may be different shapes, such as hexagonal cells, fingers, strips or waves. US2006/0145252A1 discloses a power semiconductor device comprising a plurality of transistor base cells having a four branch shape.
Document U.S. Pat. No. 6,365,931B1 presents a gate isolation structure which is suitable for isolating the gates of the above discussed power devices. FIG. 1 presents a cross-section view of the structure of the gate insulating structure. The N substrate 1 comprises an P-region 2 in which N material source regions 3 are provided. Partly above the source regions 3, the P-region 2 and the N substrate 1 a gate oxide layer 4 is provided and on a sub area of the gate oxide layer is provided an insulated gate 5 of polysilicon. On top of the gate 5 is an oxide layer deposited and at the lateral wall of the gate 5 is provided an oxide layer 9 separating the gate 5 from other layers. Around the gate 5, oxide layer 9 is provided a nitride layer 10. Adjacent to the lateral walls of the nitride layer 10 and on top of a portion of the nitride layer which is on top of the gate oxide layer 4, a oxide spacer 8 is provided and a metal layer 7 is deposited on top of the above discussed structure for forming the source contact. A backside surface (not shown) of the N substrate 1, which is a surface that is opposite the surface on which the gate oxide layer 4 is provided, is provided with a drain contact. According to the cited patent in a specific processing step, the oxide layer 9 is placed, thus, an additional process handling is used to manufacture the oxide layer 9. Additionally, the cited document proposes a thickness for the oxide layer 9 that is about equal to the thickness of the gate oxide layer 4. Depositing the oxide layer 9 is a relatively complex process step. According to the cited document, the oxide layer 9 is made during second dopant ion implantation and consequent diffusion for obtaining the source regions 3 by comprising oxidation for the oxide layers 9 formation on the sidewalls of the polysilicon layer 5.